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| st5080a piafe programmable isdn audio front end advance data features: complete codec and filter system including: pcm analog to digital and digital to analog converters powerful analog front end capa- ble to interface directly: - microphone dynamic, piezo or electrete - earpiece down to 100 w or up to 150nf - loudspeaker down to 50 w or buzzer up to 600nf. transmit band-pass filter active rc noise filter receive low-pass filter with sin x/x correction mu-law or a-law selectable com- panding coder and decoder precision voltage reference phones features: dual switchable microphone ampli- fier inputs. gain programmable: 15 db range, 1 db step. loudspeaker amplifier auxiliary output. attenuation programmable: 30 db range, 2 db step. separate earpiece amplifier output. attenuation programmable: 15 db range, 1 db step auxiliary switchable external ring input (eain). transient supression signal during power on. internal programmable sidetone circuit. attenuation programmable: 15 db range, 1 db step. internal ring or tone generator in- cluding dtmf tones, sinewave or squarewave waveforms. attenu- ation programmable: 27 db range, 3 db step. compatible with hands-free circuit tea7540. on chip switchable anti-acoustic feed-back circuit (anti-larsen). general features: extended temperature range op- eration (*) 40 c to +85 c. extended power supply range 5v 10%. 60 mw operating power (typical). 1.0 mw standby power (typical). cmos digital interfaces. single + 5v supply. digital loopback test mode. programmable digital and control interfaces: digital pcm interface associated with separate serial control interface mi- crowire ? compatible. gci interface compatible. (*) functionality guaranteed in the range 40 c to +85 c; timing and electrical specifications are guaranteed in the range 25 cto+85 c. applications: isdn terminals. digital telephones ct2 and gsm applications this is advanced information on a new product now in development or undergoing evaluation. details are subject to change without notice. december 1994 ordering number: ST5080D so28 1/32
block diagram pin connections (top view) st5080a 2/32 typical isdn telephone set application st5080a 3/32 general description st5080a piafe is a combined pcm codec/fil- ter device optimized for isdn terminals and digi- tal telephone applications. this device is a-law and mu-law selectable and offers a number of pro- grammable functions accessed through a serial control channel. depending on mode selected, channel control is provided by means of a separate serial channel control microwire compatible or multiplexed with the pcm voice data channel in a gci com- patible format requiring only 4 digital interface pins. when separate serial control interface is se- lected, pcm interface is compatible with combo i and combo ii families of devices such as etc5057/54, ts5070/71. piafe is built using sgs-thomson's advanced hcmos process. transmit section of piafe consists of an amplifier with switchable high impedance inputs followed by a programmable gain amplifier, an active rc antialiasing pre-filter to provide attenuationof high frequency noise, an 8th order switched capacitor band pass transmit filter and an a-law/mu-law se- lectable compandig encoder. receive section consist of an a-law/mu-law se- lectable expanding decoder which reconstructs the analog sampled data signal, a 3400 hz low pass filter with sin x/x correction followed by two separate programmable attenuation blocks and two power amplifiers: one can be used to drive an earpiece, and the other to drive a 50 w loud- speaker. programmable functions on piafe include a ring/tone generator which provides one or two tones and can be directed to earpiece or to loud- speaker or alternatively a piezo transducer up to 600nf. a separate programmable gain amplifier allows gain control of the signal injected. ring/tone gen- erator provides sinewave or squarewave signal with precise frequencies which may be also di- rected to the input of the transmit amplifier for dtmf tone generation. an auxiliary analog input (eain) is also provided to enable for example the output of an external band limited ring signal to the loudspeaker. transmit signal may be fed back into the receive ampifier with a programmable attenuation to pro- vide a sidetone circuitry. a switchable anti-accoustic feed-back system cancels the larsen effect in speech monitoring ap- plication. two additional pins are provided for insertion of an external handfree function in the loudspeaker receive path. an output latch controlled by register program- ming permits external device control. pin functions pin name description 1,2 hfi, hfo hands free i/os: these two pins can be used to insert an external handfree circuit such as the tea 7540 in the receive path. hfo is an output which provides the signal issued from output of the receive low pass filter while hfi is a high impendance input which is connected directly to one of the inputs of the loudspeaker amplifier. 3,4 v fr+ ,v fr receive analog earpiece amplifier complementary outputs, capable of driving load impedances between 100 and 400 w or a piezo up to 150nf. these outputs can drive directly earpiece transductor. the signal at this output can drive be the summ of: - receive speech signal from d r , - internal tone generator, - sidetone signal. 5v cc positive power supply input for the digital section. +5 v + 10%. 6,7 ls-,ls+ receive analog loudspeaker amplifier complementary outputs, intended for driving a loudspeaker: 80 mw on 50 w load impedance can be provided at low distorsion meeting specifications. alternatively this stage can drive a piezo transducer up to 600nf. the signal at these outputs can be the sum of: - receive speech signal from d r , - internal tone generator, - external input signal from eain input. st5080a 4/32 pin functions (continued) pin name description 9 ms mode select: this input selects combo i/ii interface mode with separate microwire control interface when tied high and gci mode when tied low. 10 d x transmit data ouput: data is shifted out on this pin during the assigned transmit time slots. elsewhere d x output is in the high impendance state. in combo i/ii mode, voice data byte is shifted out from tristate output d x at the mclk frequency on the rising edge of mclk. in gci mode, voice data byte and control bytes are shifted out from open-drain output d x at half the mclk. an external pull up resistor is needed. 11 n.c. no connected. 14 d r receive data input: data is shifted in during the assigned received time slots. in the combo i/ii mode, voice data byte is shifted in at the mclk frequency on the falling edges of mclk. in the gci mode, pcm data byte and contol byte are shifted in at half the mclk frequency on the receive rising edges of mclk. there is one period delay between transmit rising edge and receive rising edge of mclk. 15 fs frame sync input: this signal is a 8khz clock which defines the start of the transmit and receive frames. either of three formats may be used for this signal: non delayed timing mode, delayed timing and gci compatible timing mode. 16 mclk master clock input: this signal is used by the switched capacitor filters and the encoder/decoder sequencing logic. values must be 512 khz, 1.536 mhz, 2.048 mhz or 2.56 mhz selected by means of control register cro. mclk is used also to shift-in and out data. in gci mode, 2.56 mhz and 512 khz are not allowed. 17 lo open drain output: a logic 1 written into do (cr1) appears at lo pin as a logic 0 a logic 0 written into do puts lo pin in high impedance. 18 n.c. no connected. 21 mic2+ alternative positive high impedance input to transmit pre- amplifier. 22 mic1+ positive high impedance input to transmit pre-amplifier for microphone symetrical connection. 23 mic1- negative high impedance input to transmit pre-amplifier for microphone symetrical connection. 24 n.c. no connected. 25 v cca positive power supply input for the analog section. +5 v + 10%. v cc and v cca must be directly connected together. 26 mic2- alternative negative high impedance input to transmit pre- amplifier. 27 gnda analog ground: all analog signals are referenced to this pin. gnd and gnda must be connected together close to the device. 28 eain external auxiliary input: this input can be used to provide alternate signals to the loudspeaker in place of internal ring generator. input signal should be voice band limited. st5080a 5/32 following pin definitions are used only when combo i/ii mode with separate microwire com- patible serial control port is selected. (ms input set equal one) pin functions (continued) pin name description 12 co control data output: serial control/status information is shifted out from the piafe on this pin when cs- is low on the falling odges of cclk. 13 ci control data input: serial control information is shifted into the piafe on this pin when cs- is low on the rising edges of cclk. 19 cclk control clock input: this clock shifts serial control information into ci and out from co when the cs- input is low, depending on the current instruction. cclk may be asynchronous with the other system clocks. 20 cs- chip select input: when this pin is low, control information is written into and out from the piafe via ci and co pins. following pin definitions are used only when the gci mode is selected. (ms input set equal zero) pin functions (continued) pin name description 19,13,12,20 a0,a1,a2,a3 these pins select the address of piafe on gci interface and must be hardwired to either v cc or gnd. a0,a1,a2,a3 refer to c4,c5,c6,c7 bits of the first address byte respectively. st5080a 6/32 functional description power on initialization: when power is first applied, power on reset cicuitry initializes piafe and puts it into the power down state. gain control registers for the various programmable gain amplifiers and programmable switches are initialized as indicated in the control register description section. all codec functions are disabled. digital interface is configured in gci mode or in combo i/ii mode depending on mode select pin connection. the desired selection for all programmable func- tions may be intialized prior to a power up com- mand using monitor channel in gci mode or mi- crowire port in combo i/ii mode. power up/down control: following power-on initialization, power up and power down control may be accomplished by writ- ing any of the control instructions listed in table 1 into piafe with opo bit set to 0 for power up or 1 for power down. normally, it is recommended that all programma- ble functions be initially programmed while the device is powered down. power state control can then be included with the last programming in- struction or in a separate single byte instruction. any of the programmable registers may also be modified while st5080a is powered up or down by setting opo bit as indicated. when power up or down control is entered as a single byte instruc- tion, bit 1 must be set to a 0. when a power up command is given, all de-acti- vated circuits are activated, but output d x will re- main in the high impedance state on b time slots until the second fs pulse after power up, even if a b channel is selected. power down state: following a period of activity, power down state may be reentered by writing a power down in- struction. control registers remain in their current state and can be changed either by microwire control in- terface or gci control channel depending on mode selected. in addition to the power down instruction, detec- tion of loss mclk (no transition detected) auto- matically enters the device in oreseto power down state with d x output in the high impedance state and l0 in high impedance state. transmit section: transmit analog interface is designed in two stages to enable gains up to 35 db to be realized. stage 1 is a low noise differential amplifier provid- ing 20 db gain. a microphone may be ca- pacitevely connected to mic1+, mic1- inputs, while the mic2+ mic2 inputs may be used to capacitively connect a second microphone (for digital handsfree operation) or an auxiliary audio circuit such as tea 7540 hands-free circuit. mic1 or mic2 source is selected with bit 7 of register cr4. following the first stage is a programmable gain amplifier which provides from 0 to 15 db of addi- tional gain in 1 db step. the total transmit gain should be adjusted so that, at reference point a, see block diagram description, the internal 0 dbmo voltage is 0.739 v (overload level is 1.06 vrms). second stage amplifier can be pro- grammed with bits 4 to 7 of cr5. to temporarily mute the transmit input, bit te (6 of cr4) may be set low. in this case, the analog transmit signal is grounded and the sidetone path is also disabled. an active rc prefilter then precedes the 8th order band pass switched capacitor filter. a/d converter has a compressing characteristic according to ccitt a or mu255 coding laws, which must be selected by setting bits ma, ia in register cr0. a precision on chip voltage reference ensures accu- rate and highly stable transmission levels. any offset voltage arising in the gain-set amplifier, the filters or the comparator is cancelled by an in- ternal autozero circuit. each encode cycle begins immediatly at the be- ginning of the selected transmit time slot. the to- tal signal delay referenced to the start of the time slot is approximatively 195 m s (due to the transmit filter) plus 123 m s (due to encoding delay), which totals 320 m s. voice data is shifted out on d x dur- ing the selected time slot on the transmit rising adges of mclk. receive section: voice data is shifted into the decoder's receive voice data register via the d r pin during the se- lected time slot on the 8 receive edges of mclk. the decoder consists of an expanding dac with either a or mu255 law decoding characteristic which is selected by the same control instruction used to select the encode law during intitializa- tion. following the decoder is a 3400 hz 6th or- der low pass switched capacitor filter with integral sin x/x correction for the 8 khz sample and hold. 0 dbmo voltage at this (b) reference point (see block diagram description) is 0.49 vrms. a tran- scient suppressing circuitry ensure interference noise suppression at power up. the analog speech signal output can be routed either to earpiece (v fr+ ,v fr- outputs) or to loud- speaker (ls+, ls- outputs) by setting bits sl and se (1 and 0 of cr4). total signal delay is approximatively 190 m s (filter plus decoding delay) plus 62.5 m s (1/2 frame) which gives approximatively 252 m s. differential outputs v fr+ ,v fr- are intended to di- st5080a 7/32 rectly drive an earpiece. preceding the outputs is a programmable attenuation amplifier, which must be set by writing to bits 4 to 7 in register cr6. at- tenuations in the range 0 to -15 db relative to the maximum level in 1 db step can be programmed. the input of this programmable amplifier is the summ of several signals which can be selected by writing to register cr4.: - receive speech signal which has been de- coded and filtered, - internally generated tone signal, (tone ampli- tude is programmed with bits 4 to 7 of register cr7), - sidetone signal, the amplitude of which is pro- grammed with bits 0 to 3 of register cr5 v fr+ and v fr- outputsare capable of driving output power level up to 14mw into differentially con- nected load impedance between 100 and 400 w . differential outputs ls+,ls- are intended to di- rectly drive a loudspeaker. preceding the outputs is a programmable attenuation amplifier, which must be set by writing to bits 0 to 3 in register cr6. attenuations in the range 0 to -30 db rela- tive to the maximum level in 2.0 db step can be programmed. the input of this programmable am- plifier can be the summ of signals which can be selected by writing to register cr4: - receive speech signal which has been de- coded and filtered, - internally generated tone signal, (tone ampli- tude is programmed with bits 4 to 7 of register cr7), - eain input which may be an alternate ring signal or any voice frequency band limited signal. (an external decoupling capacitor of about 0.1 m f is necessary). receive voice signal may be directed to output hfo by means of bit hfe in register cr4. after processing, signal must be re-entered through in- put hfi to loudspeaker amplifier input. (an exter- nal decoupling capacitor of about 0.1 m f is neces- sary). ls+ and ls- outputs are capable of driving output power level up to 80 mw into 50 w differentially connected load impedance at low distortion meet- ing pcm channel specifications. when the signal source is a ring squarewave signal, power levels up to approximatively 200 mw can be delivered. anti-acoustic feed-back for loudspeaker to hand- set microphone loop with squelch effect: on chip switchable anti-larsen for loudspeaker to handset microphone feedback is implemented. a 12db depth gain control on both transmit and receive path is provided to keep constant the loop gain. on the transmit path the 12db gain control is pro- vided starting from the cr5 transmit gain defini- tion; at the same time, on the receive path the 12db gain control is provided starting from cr6 receive gain definition. digital and control interface: piafe provides a choice of either of two types of digital interface for both control data and pcm. for compatibility with systems which use time slot oriented pcm busses with a separate control in- terface, as used on combo i/ii families of de- vices, piafe functions are described in next sec- tion. alternatively, for systems in which pcm and con- trol data are multiplexed together using gci inter- face scheme, piafe functions are described in the section following the next one. piafe will automatically switch to one of these two types of interface by sensing the ms pin. due to line transceiver clock recovery circuitry, a low jitter may be provided on f s and mclk clocks. f s and mclk must be always in phase. for st5421s transceiver, as an example, maximun value of jitter amplitude is a step of 65 ns at each gci frame (125 m s). so, the maximum jitter amplitude is 130 ns pk-pk. combo i/ii mode. digital interface (fig. 1) f s frame sync input determines the beginning of frame. it may have any duration from a single cy- cle of mclk to a squarewave. two different rela- tionships may be established between the frame sync input and the first time slot of frame by set- ting bit 3 in register cr0. non delayed data mode is similar to long frame timing on etc5057/ ts5070 series of devices (combo i and combo ii respectively): first time slot begins nominally coincident with the rising edge of f s . alternative is to use delayed data mode, which is similar to short frame sync timing on combo i or combo ii, in which f s input must be high at least a half cycle of mclk earlier the frame beginning. a time slot assignment circuit on chip may be used with both timing modes, allowing connection to one of the two b1 and b2 voice data channels. two data formats are available: in format 1, time slot b1 corresponds to the 8 mclk cycles follow- ing immediately the rising edge of fs, while time slot b2 corresponds to the 8 mclk cycles follow- ing immediately time slot b1. in format 2, time slot b1 is identical to format 1. time slot b2 appears two bit slots after time slot b1. this two bits space is left available for inser- tion of the d channel data. data format is selected by bit ff (2) in register cr0. time slot b1 or b2 is selected by bit t0 (0) in control register cr1. bit en (2) in control register cr1 enables or dis- ables the voice data transfer on d x and d r as appropriate. during the assigned time slot, d x st5080a 8/32 output shifts data out from the voice data register on the rising edges of mclk. serial voice data is shifted into d r input during the same time slot on the falling edges of mclk. d x is in the high impedance tristate condition when in the non selected time slots. control interface: control information or data is written into or read- back from piafe via the serial control port con- sisting of control clock cclk, serial data input ci and output co, and chip select input, cs-. all control instructions require 2 bytes as listed in ta- ble 1, with the exception of a single byte power- up/down command. to shift control data into st5080a, cclk must be pulsed high 8 times while cs- is low. data on ci input is shifted into the serial input register on the rising edge of each cclk pulse. after all data is shifted in, the content of the input shift register is decoded, and may indicate that a 2nd byte of control data will follow. this second byte may either be defined by a second byte-wide cs- pulse or may follow the first contiguously, i.e. it is not mandatory for cs- to return high in between the first and second control bytes. at the end of figure 2: gci interface frame structure figure 1: digital interface format st5080a 9/32 the 2nd control byte, data is loaded into the ap- propriate programmable register. cs- must return high at the end of the 2nd byte. to read-back status information from piafe, the first byte of the appropriate instruction is strobed in during the first cs- pulse, as defined in table 1. cs- must be set low for a further 8 cclk cy- cles, during which data is shifted out of the co pin on the falling edges of cclk. when cs- is high, co pin is in the high imped- ance tri-state, enabling co pins of several de- vices to be multiplexed together. thus, to summarise, 2 byte read and write in- structions may use either two 8-bit wide cs- pulses or a single 16 bit wide cs- pulse. control channel access to pcm interface: it is possible to access the b channel previously selected in register cr1. a byte written into control register cr3 will be automatically transmitted from d x output in the following frame in place of the transmit pcm data. a byte written into control register cr2 will be automatically sent through the receive path to the receive amplifiers. in order to implement a continuous data flow from the control microwire interface to a b chan- nel, it is necessary to send the control byte on each pcm frame. a current byte received on d r input can be read in the register cr2. in order to implement a con- tinuous data flow from a b channel to mi- crowire interface, it is necessary to read regis- ter cr2 at each pcm frame. gci compatible mode gci interface is an european standardized inter- face to connect isdn dedicated components in the different configurations of equipment as ter- minals, network terminations, pbx, etc... in a terminal equipment, this interface called scit for special circuit interface for terminals al- lows for example connection between: - st5421 (sid-gci) and st5451 (hdlc/gci controller) used for 16 kbit/s d channel packet frames processing and sid control, - peripheral devices connected to a 64 kbit/s b channel and st5451 used for gci peripheral control. st5080a may be assigned to one of the b chan- nels present on the gci interface and is moni- tored via a control channel which is multiplexed with the 64 kbit/s voice data channels. figure 2 shows the frame structure at the gci in- terface. two 256 kbit/s channel are supported. a)gci channel 0: it is structured in four sub- channels: b1 channel 8 bits per frame b2 channel 8 bits per frame m channel 8 bits per frame ignored by piafe sc channel 8 bits per frame ignored by piafe only b1 or b2 channel can be selected in piafe for pcm data transfer. b)gci channel 1: it is structured also in four subchannels: b1* channel 8 bits per frame b2* channel 8 bits per frame m* channel 8 bits per frame sc* which is structured as follows: 6 bits ignored by piafe a* bit associated with m* channel e* bit associated with m* channel. b1* or b2* channel can be selected in piafe for pcm data transfer. m* channel and two associated bits e* and a* are used for piafe control. thus, to summarize, b1, b2, b1* or b2* channel can be selected to transmit pcm data and m* channel is used to read/write status/command pe- ripheral device registers. protocol for byte ex- change on the m* channel uses e* and a* bits. physical interface the interface is physically constitued with 4 wires: input data wire: d r output data wire: d x bit clock: mclk frame synchronization: f s data is synchronized by mclk and f s clock in- puts. f s insures reinitialization of time slot counter at each frame beginning. the rising edge or fs is the reference time for the first gci channel bit. data is transmitted in both directions at half the mclk input frequency. data is transmitted on the the rising edge of mclk and is sampled one pe- riod after the transmit rising edge, also on a rising edge. note: transmit data may be sampled by far-end device ie sid st5421 on the falling edge 1.5 pe- riod after the transmit rising edge. unused channel are high impedance. data out- puts are open-drain and need an external pull up resistor. combo activation/deactivation st5080a is automatically set in power down mode when gci clocks are idle. gci section is re- activated when gci clocks are detected. piafe is completly reactivated after receiving of a power up command. exchange protocol on m* channel st5080a 10/32 protocol allows a bidirectional transfer of bytes between st5080a and gci controller with ac- knowledgment at each received byte. for piafe, standard protocol is simplified to provide read or write register cycles almost identical to mi- crowire serial interface. write cycle control unit sends through the gci controller fol- lowing bytes: - first byte is the chip select byte. the first four bits indicate the device address: (a3,a2,a1,a0). the four last bits are ignored. st5080a compare the validated byte re- ceived internally with the address defined by pins a3, a2, a1, a0. if comparison is true, byte is acknowledged, if not, st5080a does not acknowledge the byte. note : an internal omessage in progresso flag re- mains active till the end of the complete message transmission to avoid irrelevant acknowledgement of any further byte. - second byte is structured as defined in ta- ble 1. - third byte is the data byte to write into the register as indicated in table 1. it is possible but optional to write to several differ- ent registers in a single message. in this case the chip select byte is sent only once at the begin- ning of the message, the device automatically toggles between address byte and data byte. read cycle control unit sends two bytes. first byte is the chip select byte as defined above. second byte is structured as defined in table 1. if piafe identifies a read-back cycle, bit 2 of byte 1 in table 1 equal 1, it has to respond to the con- trol unit by sending a single byte message which is the content of the addressed register. it is possible but optional to request several differ- ent read-back register cycles in a single message but it is recommended to wait the answer before requesting a new read back to avoid loss of data. st5080a responds by sending a single data byte message at each request. received byte validation: a received byte is validated if it is detected two consecutive times identical. exchange protocol: exchange protocol is identical for both directions. sender uses e* bit to indicate that it is sending a m* byte while receiver uses a* bit to acknowledge received byte. when no message is transferred, e* bit and a* bit are forced to inactive state. a transmission is initialized by sender putting e* bit from inactive state to active state and by send- ing first byte on m* channel in the same frame. transmission of a message is allowed only if a* bit from the receiver has been set inactive for at least two frames. when receiver is ready, it validates the received byte internally when received in two consecutive frames identical. then the receiver sets first a* bit from inactive to active state (pre-acknow- legement), and maintains a* bit active at least in the following frame (acknowledgement). if valida- tion is not possible, (two last bytes received are not identical), receiver aborts the message setting a* bit active for only a single frame. for the first byte received, abort sequence is not allowed. piafe does not respond either if two last bytes are not identical or if the byte received does not meet the chip select byte defined by a0-a3 pins bias. a second byte may be transmitted by the sender putting e* bit from active to inactive state and sending the second byte on the m* channel in the same frame. e* bit is set inactive for only one frame. if it remains inactive more than one frame, it is an end of message (i.e. not second byte available). the second byte may be transmitted only after re- ceiving the pre-acknowledgment of the previous byte transmitted (see fig. 3). the same protocol is used if a third byte is transmitted. each byte has to be transmitted at least in two consecutive frames. the receiver validates current received byte as done on first byte and then set a* bit in the next two frames first from active to inactive state (pre- acknowledgement), and after from inactive to ac- tive state (acknowledgement). if the receiver can- not validate the received current byte (two bytes received are not identical), it pre-acknowledges normally, but let a* bit in the inactive state in the next frame which indicates an abort request. if a message sent by st5080a is aborted, it will stop the message and wait for a new read cycle instruction from the controller. a message received by st5080a is acknow- ledged or aborted without flow control. figures 3 gives timing of a write cycle. most sig- nificant bit (msb) of a monitor byte is sent first on m* channel. e* and a* bits are active low and inactive state on dout is high impedance. programmable functions st5080a 11/32 figure 3: e and a bits timing st5080a 12/32 for both formats of digital interface, programma- ble functions are configured by writing to a num- ber of registers using a 2-byte write cycle (not in- cluding chip select byte in gci). most of these registers can also be read-back for verification. byte one is always register address, while byte two is data. table 1 lists the register set and their respective adresses. table 1: programmable register intructions function address byte data byte 76543210 single byte power up/down pxxxxx0x none write cr0 p 0 0 0 0 0 1 x see cr0 table 2 read-back cr0 p 0 0 0 0 1 1 x see cr0 write cr1 p 0 0 0 1 0 1 x see cr1 table 3 read-back cr1 p 0 0 0 1 1 1 x see cr1 write data to receive path p 0 0 1 0 0 1 x see cr2 table 4 read data from d r p001011xseecr2 write data to d x p 0 0 1 1 0 1 x see cr3 table 5 write cr4 p 0 1 0 0 0 1 x see cr4 table 6 read-back cr4 p 0 1 0 0 1 1 x see cr4 write cr5 p 0 1 0 1 0 1 x see cr5 table 7 read-back cr5 p 0 1 0 1 1 1 x see cr5 write cr6 p 0 1 1 0 0 1 x see cr6 table 8 read-back cr6 p 0 1 1 0 1 1 x see cr6 write cr7 p 0 1 1 1 0 1 x see cr7 table 9 read-back cr7 p 0 1 1 1 1 1 x see cr7 write cr8 p 1 0 0 0 0 1 x see cr8 table 10 read-back cr8 p 1 0 0 0 1 1 x see cr8 write cr9 p 1 0 0 1 0 1 x see cr9 table 11 read-back cr9 p 1 0 0 1 1 1 x see cr9 write test register cr10 p 1 0 1 0 0 1 x reserved note 1: bit 7 of the address byte and data byte is always the first bit clocked into or out from: ci and co pins when microwire serial port is enabled, or into and out from d r and d x pins when gci mode selected. x = reserved: write 0 note 2: opo bit is power up/down control bit. p = 1 means power down. bit 1 indicates, if set, the presence of a second byte. note 3: bit 2 is write/read select bit. st5080a 13/32 table 2: control register cr0 functions 76543210 function f1 f0 ma ia dn ff b7 dl 0 0 1 1 0 1 0 1 mclk = 512 khz mclk = 1.536 mhz mclk = 2.048 mhz mclk = 2.560 mhz * (1) (1) 0 1 1 x 0 1 select mu-255 law a-law including even bit inversion a-law; no bit inversion * 0 1 delayed data timing non delayed data timing * (1) (1) 0 1 b1 and b2 consecutive b1 and b2 separated * (1) (1) 0 1 8 bits time-slot 7 bits time-slot * 0 1 normal operation digital loop-back * *: state at power on initialization (1): significant in combo i/ii mode only table 3: control register cr1 functions 76543210 function hfe ale do mr mx en t1 t0 0 1 hfo / hfi pins disabled hfo / hfi pins enabled * 0 1 anti-larsen disabled anti-larsen enabled * 0 1 l0 latch is put in high impedance l0 latch set to 0 * 0 1 d r connected to rec. path cr2 connected to rec. path * (1) (1) 0 1 trans path connected to d x cr3 connected to d x * (1) (1) 0 1 voice data transfer disable voice data transfer enable * 0 0 1 1 0 1 0 1 b1 channel selected b2 channel selected b1* channel selected b2* channel selected * (2) (2) *: state at power on initialization (1): significant in combo i / ii mode only (2): significant in gci mode only. st5080a 14/32 table 4: control register cr2 functions 76543210 function d7 d6 d5 d4 d3 d2 d1 d0 msb lsb data sent to receive path or data received from d r input table 5: control registers cr3 functions 76543210 function d7 d6 d5 d4 d3 d2 d1 d0 msb lsb d x data transmitted table 6: control register cr4 functions 76543210 function vs te si ee rtl rte sl se 0 1 mic1 selected mic2 selected * 0 1 transmit input muted transmit input enabled * 0 1 internal sidetone disabled internal sidetone enabled * 0 1 eain disconnected eain selected to loudspeaker * 0 0 1 1 0 1 0 1 ring / tone muted ring / tone to earpiece ring / tone to loudspeaker ring / tone to earpiece and loudspeaker * 0 0 1 1 0 1 0 1 receive signal muted receive signal connected to earpiece amplifer receive signal connected to loudspeaker amplifier receive signal connected to loudspeaker and earpiece amplifier * *: state at power on initialization st5080a 15/32 table 7: control register cr5 functions 76543210 function transmit amplifier sidetone amplifier 0 0 - 1 0 0 - 1 0 0 - 1 0 1 - 1 0 db gain 1 db gain in 1 db step 15 db gain * 0 0 - 1 0 0 - 1 0 0 - 1 0 1 - 1 -12.5 db gain -13.5 db gain in 1 db step -27.5 db gain * *: state at power on initialization table 8: control register cr6 functions 76543210 function earpiece ampifier loudspeaker 0 0 - 1 0 0 - 1 0 0 - 1 0 1 - 1 0 db gain -1 db gain in 1 db step -15 db gain * 0 0 - 1 0 0 - 1 0 0 - 1 0 1 - 1 0 db gain -2 db gain in 2 db step -30 db gain * *: state at power on initialization st5080a 16/32 table 9: control register cr7 functions 76543210 function tone gain f1 f2 sn de attenuation f1 v pp f2 v pp 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 x x 0 0 1 1 0 0 1 1 x x 0 1 0 1 0 1 0 1 0 1 .... 0db * -3 db -6 db -9 db -12 db -15 db -18 db -21 db -24 db -27 db ... 2.4 (1) 1.70 1.20 0.85 0.60 0.43 0.30 0.21 0.15 0.10 .... 1.9 (1) 1.34 0.95 0.67 0.47 0.34 0.24 0.17 0.12 0.08 0 0 1 1 0 1 0 1 f1 and f2 muted f2 selected f1 selected f1 and f2 in summed mode * 0 1 squarewave signal selected sinewave signal selected * 0 1 normal operation tone / ring generator connected to transmit path * *: state at power on initialization (1): value provided if f1 or f2 is selected alone. if f1 and f2 are selected in the summed mode, f1=1.34 v pp while f2=1.06 v pp . output generator is 2.4 v pp x reserved: write 0 table 10: control register cr8 functions 76543210 function f17 f16 f15 f14 f13 f12 f11 f10 msb lsb binary equivalent of the decimal number used to calculate f1 table 11: control register cr9 functions 76543210 function f27 f26 f25 f24 f23 f22 f21 f20 msb lsb binary equivalent of the decimal number used to calculate f2 st5080a 17/32 control register cr0 first byte of a read or a write instruction to control register cr0 is as shown in table 1. second byte is as shown in table 2. master clock frequency selection a master clock must be provided to piafe for op- eration of filter and coding/decodingfunctions. in combo i/ii mode, mclk frequency can be either 512 khz, 1.536 mhz, 2.048 mhz or 2.56 mhz. bit f1 (7) and f0 (6) must be set during initializa- tion to select the correct internal divider. in gci mode, mclk must be either 1.536mhz or 2.048mhz. 512khz and 2.56mhz are not allowed. default value is 1.536 mhz for both modes. any clock different from the default one must be selected prior a power-up instruction for both modes. coding law selection bits ma (5) and ia (4) permit selection of mu-255 law or a law coding with or without even bit inver- sion. after power on initialization, the mu-255 law is se- lected. digital interface timing bit dn=0 (3) selects digital interface in delayed timing mode while dn=1 selects non delayed data timing. in gci mode, bit dn is not significant. after reset and if combo i/ii mode is selected, delayed data timing is selected. digital interface format bit ff=0 (2) selects digital interface in format 1 where b1 and b2 channel are consecutive. ff=1 selects format 2 where b1 and b2 channel are separated by two bits. (see digital interface format section). in gci mode, bit ff is not significant. 56+8 selection bit 'b7' (1) selects capability for piafe to take into account only the seven most significant bits of the pcm data byte selected. when 'b7' is set, the lsb bit on d r is ignored and lsb bit on d x is high impedance. this function al- lows connection of an external oin bando data generator directly connected on the digital inter- face. digital loopback digital loopback mode is entered by setting dl bit(0) equal 1. in digital loopback mode, data written into re- ceive pcm data register from the selected re- ceived time-slot is read-back from that register in the selected transmit time-slot on d x . time slot is selected with register cr1. no pcm decoding or encoding takes place in this mode. transmit and receive amplifier stages are muted. control register cr1 first byte of a read or a write instruction to control register cr1 is as shown in table 1. second byte is as shown in table 3. hands-free i/os selection bit hfe set to one enables hfi, hfo pins for connection of an external handfree circuit such as tea 7540. hfo is an analog output that provides the receive voice signal. 0 dbmo level on that output is 0.491 vrms (1.4v pp ). hfi is an analog high impedance input (10 k w typ.) intended to send back the processed receive signal to the loudspeaker. 0 dbmo level on that input is 0.491vrms. anti-larsen selection bit ale set to one enables on-chip antilarsen and squelch effect system. latch output control bit do controls directly logical status of latch out- put lo: ie, a ozeroo written in bit do puts output lo in high impedance, a ooneo written in bit do sets output lo to zero. mu 255 law true a law even bit inversion a law without even bit inversion msb lsb msb lsb msb lsb vin = + full scale 1 0 0000001010101011111111 vin = 0 v 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vin = - full scale 0 0 0000000010101001111111 msb is always the first pcm bit shifted in or out of piafe. st5080a 18/32 microwire access to b channel on receive path bit mr (4) selects access from microwire register cr2 to receive path. when bit mr is set high, data written to register cr2 is decoded each frame, sent to the receive path and data in- put at d r is ignored. in the other direction, current pcm data input re- ceived at d r can be read from register cr2 each frame. microwire access to b channel on transmit path bit mx (3) selects access from microwire write only register cr3 to d x output. when bit mx is set high, data written to cr3 is output at d x every frame and the output of pcm encoder is ignored. b channel selection bit 'en' (2) enables or disables voice data trans- fer on d x and d r pins. when disabled, pcm data from dr is not decoded and pcm time-slots are high impedance on d x . in gci mode, bits 't1' (1) and 't0' (0) select one of the four channels of the gci interface. in combo i/ii mode, only b1 or b2 channel can be selected according to the interface format se- lected. bit 't1' is ignored. control register cr2 data sent to receive path or data received from d r input. refer to bit mr(4) in ocontrol register cr1o paragraph. control register cr3 d x data transmitted. refer to bit mx(3) in ocontrol rgister cr1o paragraph. control register cr4 first byte of a read or a write instruction to control register cr4 is as shown in table 1. second byte is as shown in table 6. transmit input selection mic1 or mic2 source is selected with bit vs (7). transmit input selected can be enabled or muted with bit te (6). transmit gain can be adjusted within a 15 db range in 1 db step with register cr5. sidetone select bit osio (5) enables or disables sidetone circuitry. when enabled, sidetone gain can be adjusted with register (cr5). when transmit path is dis- abled, bit te set low, sidetone circuit is also dis- abled. external auxiliary signal select bit oeeo (4) set to one connects eain input to the loudspeaker amplifier input. ring/tone signal routing bits ortlo (3) and rte (2) provide select capabil- ity to connect on-chip ring/tone generator either to loudspeaker amplifier input or to earpiece am- plifier input or both. pcm receive data routing bits oslo (1) and oseo (0) provide select capability to connect received speech signal either to loud- speaker amplifier input or to earpiece amplifier in- put or both. control register cr5 first byte of a read or a write instuction to control register cr5 is as shown in table 1. second byte is as shown in table 7. transmit gain selection transmit amplifier can be programmed for a gain from 0db to 15db in 1db step with bits 4 to 7. 0 dbmo level at the output of the transmit ampli- fier (a reference point) is 0.739 vrms (overload voltage is 1.06 vrms). sidetone attenuation selection transmit signal picked up after the switched ca- pacitor low pass filter may be fed back into the receive earpiece amplifier. attenuation of the signal at the output of the sidetone attenu ator can be programmed from 12.5db to -27 .5db relative to reference point a in 1 db step with bits 0 to 3. control register cr6 first byte of a read or a write instruction to control register cr6 is as shown in table 1. second byte is as shown in table 8. earpiece amplifier gain selection: earpiece receive gain can be programmed in 1 db step from 0 db to -15 db relative to the maxi- mum with bits 4 to 7. 0 dbmo voltage at the output of the amplifier on pins v fr+ and v fr- is then 824.5 mvrms when 0db gain is selected down to 146.6 mvrms when 15 db gain is selected. loudspeaker amplifier gain selection: loudspeaker receive amplifier gain can be pro- grammed in 2 db step from 0 db to -30 db rela- tive to the maximum with bits 0 to 3. 0 dbmo voltage on the output of the amplifier on pins ls+ and ls- on 50 w is then 1.384 vrms (3.91v pp ) when 0 db gain is selected down to 43.7 mvrms (123.6mv pp ) when -30 db gain is se- lected. st5080a 19/32 current limitation is approximatively 150 mapk. control register cr7: first byte of a read or a write instruction to control register cr7 is as shown in table 1. second byte is as shown in table 9. tone/ring amplifier gain selection output level of ring/tone generator, before at- tenuation by programmable attenuator is 2.4 vpk- pk when f1 generator is selected alone or summed with the f2 generator and 1.9 vpk-pk when f2 generatoris selected alone. selected output level can be attenuated down to -27 db by programmable attenutator by setting bits 4 to 7. frequency mode selection bits 'f1' (3) and 'f2' (2) permit selection of f1 and/or f2 frequency generator according to ta- ble 9. when f1 (or f2) is selected, output of the ring/tone is a squarewave (or a sinewave) signal at the frequency selected in the cr8 (or cr9) register. when f1 and f2 are selected in summed mode, output of the ring/tone generator is a signal where f1 and f2 frequency are summed. in order to meet dtmf specifications, f2 output level is attenuated by 2db relative to the f1 output level. frequency temporization must be controlled by the microcontroller. waveform selection bit 'sn' (1) selects waveform of the output of the ring/tone generator. sinewave or squarewave signal can be selected. dtmf selection bit de (0) permits connection of ring/tone/dtmf generator on the transmit data path instead of the transmit amplifier output. earpiece feed-back may be provided by sidetone circuitry by setting bit si or directly by setting bit rte in register cr4. loudspeaker feed-back may be provided di- rectly by setting bit rtl in register cr4. control registers cr8 and cr9 first byte of a read or a write instruction to control register cr8 or cr9 is as shown in ta- ble 1. second byte is respectively as shown in table 10 and 11. tone or ring signal frequency value is defined by the formula: f1 = cr8 / 0.128 hz and f2 = cr9 / 0.128 hz where cr8 and cr9 are decimal equivalents of the binary values of the cr8 and cr9 registers respectively. thus, any frequency between 7.8 hz and 1992 hz may be selected in 7.8 hz step. table 12 gives examples for the main frequen- cies usual for tone or ring generation. st5080a 20/32 power supplies while pins of piafe device are well protected against electrical misuse, it is recommended that the standard cmos practise of applying gnd be- fore any other connections are made should al- ways be followed. in applications where the printed circuit card may be plugged into a hot socket with power and clocks already present, an extra long ground pin on the connector should be used. to minimize noise sources, all ground connec- tions to each device should meet at a common point as close as possible to the gnd pin in order to prevent the interaction of ground return cur- rents flowing through a common bus impedance. a power supply decoupling capacitor of 0.1 m f should be connected from this common point to v cc as close as possible to the device pins. table 12: examples of usual frequency selection description f1 value (decimal) theoric value (hz) typical value (hz) error % tone 250 hz tone 330 hz tone 425 hz tone 440 hz tone 800 hz tone 1330 hz 32 42 54 56 102 170 250 330 425 440 800 1330 250 328.2 421.9 437.5 796.9 1328.1 .00 .56 .73 .56 .39 .14 dtmf 697 hz dtmf 770 hz dtmf 852 hz dtmf 941 hz dtmf 1209 hz dtmf 1336 hz dtmf 1477 hz dtmf 1633 hz 89 99 109 120 155 171 189 209 697 770 852 941 1209 1336 1477 1633 695.3 773.4 851.6 937.5 1210.9 1335.9 1476.6 1632.8 .24 +.44 .05 .37 +.16 .01 .00 .00 sol la si do re mi flat mi fa fa sharp sol sol sharp la si do re mi 50 56 63 67 75 80 84 89 95 100 106 113 126 134 150 169 392 440 494 523.25 587.33 622.25 659.25 698.5 740 784 830.6 880 987.8 1046.5 1174.66 1318.5 390.6 437.5 492.2 523.5 586.0 625.0 656.3 695.3 742.2 781.3 828.2 882.9 984.4 1046.9 1171.9 1320.4 .30 .56 .34 +.04 .23 +.45 .45 .45 +.30 .34 .29 +.33 .34 +.04 .23 +.14 st5080a 21/32 timing diagram non delayed data timing mode delayed data timing mode st5080a 22/32 timing diagram (continued) gci timing mode serial control timing (microwire mode) st5080a 23/32 timing specifications (unless otherwise specified, v cc = 5v + 10%, t a = 25 cto 85 c; typical characteristics are specified v cc = 5v, t a =25 c; all signals are referenced to gnd, see note 5 for timing definitions) master clock timing symbol parameter test condition min. typ. max. unit f mclk frequency of mclk selection of frequency is programmable (see table 2) 512 1.536 2.048 2.560 khz mhz mhz mhz t wmh period of mclk high measured from v ih to v ih 80 ns t wml period of mclk low measured from v il to v il 80 ns t rm rise time of mclk measured from v il to v ih 30 ns t fm fall time of mclk measured from v ih to v il 30 ns pcm interface timing (combo i / ii and gci modes) symbol parameter test condition min. typ. max. unit t hmf hold time mclk low to fs low 10 ns t sfm setup time, fs high to mclk low 30 ns t dmd delay time, mclk high to data valid load = 100 pf 100 ns t dmz delay time, mclk low to dx disabled 15 100 ns t dfd delay time, fs high to data valid load = 100 pf ; applies only if fs rises later than mclk rising edge in non delayed mode only 100 ns t sdm setup time, d r valid to mclk receive edge 20 ns t hmd hold time, mclk low to d r invalid 20 ns absolute maximum ratings parameter value unit v cc to gnd 7v current at v mic (v cc 5.5v) 50 ma current at v rxo and ls + 100 ma current at any digital output + 50 ma voltage at any digital input (v cc 5.5v); limited at + 50ma v cc + 1 to gnd - 1 v storage temperature range - 65 to + 150 c lead temperature (wave soldering, 10s) + 260 c st5080a 24/32 serial control port timing (usual combo i / ii mode only) symbol parameter test condition min. typ. max. unit f cclk frequency of cclk 2.048 mhz t wch period of cclk high measured from v ih to v ih 160 ns t wcl period of cclk low measured from v il to v il 160 ns t rc rise time of cclk measured from v il to v ih 50 ns t fc fall time of cclk measured from v ih to v il 50 ns t hcs hold time, cclk high to cs low 10 ns t ssc setup time, cs low to cclk high 50 ns t sdc setup time, ci valid to cclk high 50 ns t hcd hold time, cclk high to ci invalid 50 ns t dcd delay time, cclk low to co data valid load = 100 pf , plus 1 lsttl load 80 ns t dsd delay time, cslow to co data valid 50 ns t ddz delay time cshigh or 8th cclk low to co high impedance whichever comes first 15 80 ns t hsc hold time, 8th cclk high to cs high 100 ns t scs set up time, cs high to cclk high 100 ns note 5: a signal is valid if it is above v ih or below v il and invalid if it is between v il and v ih . for the purpoes of this specification the following conditions apply: a) all input signal are defined as: v il = 0.4v, v ih = 2.7v, t r < 10ns, t f < 10ns. b) delay times are measured from the inputs signal valid to the output signal valid. c) setup times are measured from the data input valid to the clock input invalid. d) hold times are measured from the clock signal valid to the data input invalid. electrical characteristics (unless otherwise specified, v cc = 5v + 10%, t a = 25 cto 85 c; typical characteristic are specified at v cc = 5v, t a =25 c ; all signals are referenced to gnd) digital interfaces symbol parameter test condition min. typ. max. unit v il input low voltage all digital inputs dc ac 0.7 v 0.4 v v ih input high voltage all digital inputs dc ac 2.0 v 2.7 v v ol output low voltage d x ,i l = -2.0ma; dc all other digital outputs, ac i l = 1ma 0.4 0.7 v v v oh output high voltage d x ,i l = 2.0ma; dc all other digital outputs, ac i l = 1ma 2.4 2.0 v v i il input low current any digital input, gnd < v in amplitude response receive path symbol parameter test condition min. typ. max. unit g rae receive gain absolute accuracy receive gain programmed for maximum apply 0 db m0 pcm code to d r measure v fr+ -0.3 0.3 db g ral receive gain absolute accuracy receive gain programmed for maximum apply 0 db m0 pcm code to d r measure l s+ -0.6 0.6 db g rage receive gain variation with programmed gain measure earpiece gain over the range from maximum to minimum setting. calculate the deviation from the programmed gain relative to grae, i.e. g rage =g actual -g prog. -g rae -0.5 0.5 db g ragl receive gain variation with programmed gain measure loudspeaker gain over the range from maximum to minimum setting. calculate the deviation from the programmed gain relative to gral, i.e. g ragl =g actual -g prog. -g ral -1.0 1.0 db g rat receive gain variation with temperature measured relative to gra. (ls and v fr ) g r = maximum gain -0.1 0.1 db g rav receive gain variation with supply measured relative to gra. (ls and v fr ) g r = maximum gain -0.1 0.1 db g raf receive gain variation with frequency (earpiece or loudspeaker) relative to 1015,625 hz, multitone test technique used. min. gain < g r < max. gain f = 200 hz f = 300 hz to 3000 hz f = 3400 hz f = 4000 hz -0.3 -0.3 -0.8 0.3 0.3 0.0 -14 db db db db g ral e receive gain variation with signal level (earpiece) sinusoidal test method reference level = 10 dbm0 d r = 0 dbm0 to +3 dbm0 d r = -40 dbm0 to 0 dbm0 d r = -50 dbm0 to -40 dbm0 d r = -55 dbm0 to -50 dbm0 -0.25 -0.25 -0.5 -1.2 0.25 0.25 0.5 1.2 db db db db g ral l receive gain variation with signal level (loudspeaker) sinusoidal test method reference level = 10 dbm0 d r = 0 dbm0 to +3 dbm0 d r = -40 dbm0 to 0 dbm0 d r = -50 dbm0 to -40 dbm0 d r = -55 dbm0 to -50 dbm0 -0.25 -0.25 -0,5 -1.2 0.25 0.25 0.5 1.2 db db db db st5080a 28/32 envelope delay distortion with frequency symbol parameter test condition min. typ. max. unit dxa tx delay, absolute f = 1600 hz 320 m s dxr tx delay, relative f = 500 - 600 hz f = 600 - 800 hz f = 800 - 1000 hz f = 1000 - 1600 hz f = 1600 - 2600 hz f = 2600 - 2800 hz f = 2800 - 3000 hz 225 125 50 20 55 80 130 m s m s m s m s m s m s m s dra rx delay, absolute f = 1600 hz 252 m s drr rx delay, relative f = 500 - 1000 hz f = 1000 - 1600 hz f = 1600 - 2600 hz f = 2600 - 2800 hz f = 2800 - 3000 hz 10 30 105 135 185 m s m s m s m s m s noise symbol parameter test condition min. typ. max. unit nxc tx noise, c weighted v mic = 0v max. gain 16 dbrnc0 nxp tx noise, p weighted v mic = 0v max. gain -70 dbm0p nrec rx noise, c weighted (earpiece) receive pcm code = alternating positive and negative code max. gain 18 dbrnc0 nrep rx noise, p weighted (earpiece) receive pcm code = positive zero max. gain -70 dbm0p nrlc rx noise, c weighted (loudspeaker) receive pcm code = alternating positive and negative code max. gain 21 dbrnc0 nrlp rx noise, p weighted (loudspeaker) receive pcm code = positive zero max. gain -67 dbm0p nrs noise, single frequency v mic = 0v, loop-around measurament from f = 0 hz to 100 khz -50 dbm0 ppsrx positive psrr, tx v mic = 0v, v cc = 5.0 v dc + 100 mv rms ; f = 0hz to 50khz 30 db ppsrp positive psrr, rx pcm code equals positive zero, v cc = 5.0 vdc + 100 mvrms, measure v fr+ f=0hz-4khz f = 4 khz - 50 khz 30 30 30 db db db sos spurious out-band signal at the output dr input set to 0 dbm0 pcm code 300 - 3400 hz input pcm code applied at dr 4600 hz - 5600 hz 5600 hz - 7600 hz 7600 hz - 8400 hz 8400 hz - 100 khz -40 -50 -50 -50 db db db db st5080a 29/32 distortion symbol parameter test condition min. typ. max. unit s tdx s tdr signal to total distortion sinusoidal test methode (measured using c message weighting filter) level = 0 dbm0 to - 20 dbm0 level = - 20 to -30 dbm0 level = - 40 dbm0 level = - 45 dbm0 37 36 29 24 dbc dbc dbc dbc s dfx single frequency distortion transmit 0 dbm0 input signal -46 db s dfr single frequency distortion receive 0 dbm0 input signal -46 db imd intermodulation loop-around measurament voltage at v mic = -4 dbm0 to -21 dbm0, 2 frequencies in the range 300 - 3400 hz -41 db crosstalk symbol parameter test condition min. typ. max. unit c tx-r transmit to receive transmit level = 0 dbm0, f = 300 - 3400 hz dr = quietpcm code -65 db c tr-x receive to transmit receive level = 0 dbm0, f = 300 - 3400 hz v mic =0v -65 db application note for microphone connections the 4 connection modes (since the mixed mode is symmetrical with respect to mic1 and mic2) allow one microphone at a time to be selected via the v s bit (bit 7 of control register cr4). st5080a 30/32 so28 package mechanical data dim. mm inch min. typ. max. min. typ. max. a 2.65 0.104 a1 0.1 0.3 0.004 0.012 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 c 0.5 0.020 c1 45 (typ.) d 17.7 18.1 0.697 0.713 e 10 10.65 0.394 0.419 e 1.27 0.050 e3 16.51 0.65 f 7.4 7.6 0.291 0.299 l 0.4 1.27 0.016 0.050 s8 (max.) st5080a 31/32 information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications men- tioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without ex- press written approval of sgs-thomson microelectronics. ? 1994 sgs-thomson microelectronics - all rights reserved sgs-thomson microelectronics group of companies australia - brazil - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thaliand - united kingdom - u.s.a. st5080a 32/32 |
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